Abstract: With the improvement of IC technology level, the number of functional units that can be integrated on a single chip is increasing, and the total power consumption of the circuit is becoming higher and higher, especially the power consumption problem of VLSI design has become unavoidable. To solve this problem, a low-power design process based on Unified Power Format (UPF) is proposed. In view of the feature that UPF analysis mainly consists of data table operations, an algorithm based on WCOJ (Worst-Case Optimal Join) is proposed to check and merge the design rules of the power supply state table of each hierarchy in the voltage domain, and a power supply state analysis tool in low power design analyzer is designed and implemented. The experimental results show that the proposed algorithm has lower spatial complexity and time complexity than the binary merge algorithm, and has strong portability, which has important theoretical and practical significance.

Key words: low-power design, power supply state table, worst-case optimal join(WCOJ) algorithm