Abstract: A low-power transmitter driver for chiplet interconnection was designed and experimentally implemented based on the inter-chip interconnection standard proposed by the UCIe protocol. The driver circuit adopts a source series terminated (SST) driver, whose power consumption is only 1/4 that of the current mode logic (CML) structure. In addition, based on adjustable feedforward equalization technology, the driver circuit adjusts the equalization strength for different channel attenuations. By de-emphasizing equalization, it enhances the quality of the transmitted signal, ultimately reducing inter-symbol interference. This circuit was designed under CMOS 28 nm process. The front-end simulation results show that the maximum equalization intensity is -3.7 dB when the 0.9 V voltage is supplied. When the 32 Gbps NRZ signal passes through the 21 mm channel (the attenuation at the 16 GHz Nyquist frequency is -2.37 dB), after adjusting the appropriate equalization intensity, the eye height of the output waveform eye diagram is 253 mV (71.8%), the eye width is 27 ps (87%), and the simulation power consumption is only 4.0 mW.

Key words: Chiplet, feedforward equalizer(FFE), source series terminated(SST) driver, serDes, transmitter