Abstract: As the first commercial cryptographic algorithm in China, SM4 algorithm is widely used in data encryption storage and information encryption communication and other fields due to its advantages of simple and easy implementation of algorithm structure, fast encryption and decryption speed and high security. With the variable pipeline stage SM4 encryption and decryption algorithm hardware design and FPGA implementation as the research topic, this study focuses on the performance differences in designs with different pipeline stages. A controllable pipeline stage SM4 encryption and decryption circuit is designed and encapsulated into an IP core with AXI and APB interfaces. Based on XILINX ZYNQ devices, a small SoC is constructed on the XILINX ZYNQ-7020 development board, and the designed SM4 IP core is mounted onto the AXI bus for simulating real-world scenarios and conducting performance tests. The correctness of the design functionality is verified by comparing software encryption and decryption data with simulated data. Testing the performance of different pipeline stages helps identify the most suitable pipeline stage number.

Key words: SM4, pipeline design, ZYNQ, AXI, APB