Abstract: The RISC-V architecture, with its open and modular instruction set architecture (ISA) design, facilitates the integration of customized instructions tailored to specific applications and their software ecosystems, enabling efficient processing of complex algorithms and repetitive operations. However, designing acceleration instructions for RISC-V processors presents significant challenges, primarily due to limitations in operand quantity. Traditional acceleration methods typically adopt a 2-input-1- output model, which restricts the flexibility and efficiency of complex operations. To address these limitations, this method proposes a multi-operand acceleration mechanism that breaks the conventional 2-input-1-output constraint by providing a flexible interface for multiple inputs and outputs. The mechanism is validated through benchmark tests on an FPGA platform, including SHA-256, SHA-1, and FIR/IIR filter algorithms, conducted on Western Digital’s open-source RISC-V VeeR EH1 core. Experimental results demonstrate a performance improvement of up to 14% while maintaining hardware overhead at or below 3%. Compared to traditional 2-input-1-output acceleration methods, the proposed enhanced instruction set design significantly enhances the processing efficiency of RISC-V cores, demonstrating its superior capability in embedded computing and domain-specific acceleration applications.

Key words: reduced instruction set computer-V（RISC-V）, custom instructions, hardware-software co-design