Abstract: Privacy computing technology serves as a crucial means to ensure data security in data centers.With the advancement of quantum computing,lattice-based post-quantum algorithms and fully homomorphic encryption algorithms have gradually gained prominence.In these algorithms,modular arithmetic serves as one of the widely used nonlinear operations,primarily employed to prevent overflow during computations.This paper addresses the extensively utilized modular arithmetic in privacy computing and cryptographic applications,proposing a hardware-software co-design acceleration framework implemented on FPGA platforms via PCIe interfaces.The framework effectively masks communication latency and supports modular operations of up to 2 048 bits—including modular multiplication and modular exponentiation—to serve data center scenarios with privacy computing requirements.While existing researches primarily focus on modular operations themselves,our co-designed framework delivers a comprehensive acceleration solution that encompasses not only computational cores but also data interfaces,hardware-software interaction mechanisms,and optimized communication latency mitigation.Finally,we implement a tailored acceleration application for a specific telecom operator scenario,experimentally demonstrating the performance advantages of the proposed system.

Key words: privacy computing, modular multiplication, modular exponentiation, hardware-software co-design, RSA