| [1] |
CHEN Xiao-wen, RUI Zhi-chao, ZHU Qi-jin, DONG Yu, MENG Yu, .
Design and FPGA implementation of a high-precision double step branching hybrid CORDIC algorithm
[J]. Computer Engineering & Science, 2024, 46(12): 2099-2108.
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| [2] |
YANG Hang, SHAN Rui, YANG Kun, CUI Xin-yue.
Parallel implementation of a 3D-HEVC intra prediction algorithm based on dynamic self-reconfiguration structure
[J]. Computer Engineering & Science, 2024, 46(11): 1931-1939.
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| [3] |
ZHOU Zhi, GAO Jian-hua, JI Wei-xing.
Optimization of sparse matrix-vector multiplication based on FPGA and row folding
[J]. Computer Engineering & Science, 2024, 46(08): 1340-1348.
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| [4] |
CHEN Tian-yu, LI Chuan, WANG Yan-hui.
Design of high-speed BGA and PCB transmission structure for extended Chiplet application
[J]. Computer Engineering & Science, 2024, 46(06): 976-983.
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| [5] |
LI Liu-hui, WANG Liang, YANG Chun-yan, CHEN Yi-long, CHEN Peng.
Preparation and high-precision assembly technique of CCGA devices
[J]. Computer Engineering & Science, 2024, 46(05): 794-800.
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| [6] |
QIN Wen-qiang, WU Zhong-cheng, ZHANG Jun, LI Fang, .
Design of convolutional neural network acceleration system based on heterogeneous platform
[J]. Computer Engineering & Science, 2024, 46(01): 12-20.
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| [7] |
LIU Xiao-hang, JIANG Jing-fei, XU Jin-wei.
A fused-layer attention model accelerator based on systolic array
[J]. Computer Engineering & Science, 2023, 45(05): 802-809.
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| [8] |
HU Yi-hong, MA De-sheng, XU Nuo, WANG Wen-qing, HUANG Cheng-long, FANG Liang.
Stateful logic computation in three-dimensional memristor crossbar array
[J]. Computer Engineering & Science, 2023, 45(03): 381-389.
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| [9] |
JU Xin, CAO Ya-song, WEN Mei, WANG Zhi, FENG Jing.
A systolic array optimization strategy for switching matrix blocks in advance
[J]. Computer Engineering & Science, 2023, 45(01): 1-9.
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| [10] |
CUI Xin-yue, JIANG Lin, YANG Kun, HUI Chao, HU Chuan-zhan, ZHAO Jing.
A dynamic self-reconfigurable implementation method of HEVC intra prediction algorithm
[J]. Computer Engineering & Science, 2022, 44(12): 2120-2127.
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| [11] |
CHEN Xiao-fan, YANG Zhi-jie, PENG Ling-hui, WANG Shi-ying, ZHOU Gan, LI Shi-ming, KANG Zi-yang, WANG Yao, SHI Wei, WANG Lei.
A verification framework of network on chip for neuromorphic processors
[J]. Computer Engineering & Science, 2022, 44(05): 769-778.
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| [12] |
WANG Jian, ZHANG Hui-xin, .
Design of universal flight parameter testing system for semi-physical simulation flight platform
[J]. Computer Engineering & Science, 2022, 44(03): 516-520.
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| [13] |
CHEN Hao-min, YAO Sen-jing, XI Yu, ZHANG Fan, XIN Wen-cheng, WANG Long-hai, REN Chao.
Design and FPGA implementation of YOLOv3-tiny hardware acceleration
[J]. Computer Engineering & Science, 2021, 43(12): 2139-2149.
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| [14] |
ZHANG Ling.
Fault-tolerant design for daisy chain of MEDA biochip
[J]. Computer Engineering & Science, 2021, 43(07): 1192-1199.
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| [15] |
SU Zi-pei, YANG Xin, CHEN Di-hu, SU Tao.
A CNN accelerator based on 3D scalable PE array
[J]. Computer Engineering & Science, 2021, 43(03): 389-397.
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