Abstract:

This paper presents an efficient general-purpose QC-LDPC decoder architecture by combining hardware with software. The proposed architecture can be applied to regular and irregular QC-LDPC codes of various rates, lengths and parity-check matrix structures, and supports min-sum approximation decoding algorithms and realizes different message passing scheduling strategies. Some complicated message update is implemented by a hardware accelerator, thus the decoding throughput is improved. According to the quasi-cyclic structure of the parity-check matrix, the messages are stored and processed by blocks in decoding. Parallel message processing can also be realized with a small increase in implementation complexity.

Key words: decoder architecture, quasi-cyclic LDPC codes, Min-Sum approximation, message passing scheduling