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• 2014, No. 05　Published:25 May 2014 Last issue    Next issue
  Columns in this issue: 论文
• 论文

  An occupancy-based online architecture
  vulnerability factor computing method        

  PAN Songjun1,2,CHEN Chuanpeng1

  2014, 36(05): 779-785. doi:

  Abstract ( 140 )   PDF (976KB) ( 296 )   　　

  As CMOS technology scales into the nanometer era, more transistors can be integrated in a single chip, which makes microprocessors become more vulnerable to highenergy particle induced soft errors. Quantitatively analysis of the Architectural Vulnerability Factor (AVF) of different structures is an important method to guide the microprocessor reliable design. Online AVF computing techniques utilize the features that AVF varies significantly across different workloads and individual structures, and then make a tradeoff between system reliability and performance. The paper proposes an occupancybased online AVF computing method, and evaluates it with a cycleaccurate simulator SimAlpha. Experimental results on SPEC CPU2000 integer benchmark suite show that the proposed method can compute AVF efficiently for different structures. Compared with an offline method, the averaged absolute errors of AVF for issue queue, reorder buffer, and load/store queue are 0.10, 0.01, and 0.039 respectively.

  Effect of channel width and length shrinking on
  hot carrier effect in bulk and SOI nMOSFETs      

  CHI Yaqing1,2,LIU Rongrong1,CHEN Jianjun1

  2014, 36(05): 786-789. doi:

  Abstract ( 141 )   PDF (647KB) ( 283 )   　　

  The effect of channel width and length shrinking on hot carrier effect (HCE) in standard bulk Si CMOS and SOI CMOS nMOSFETs is studied.The experimental results show that the HCE degradation enhances with the decrease of channel length both in the standard bulk Si and SOI nMOSFETs.However,the channel width shrinking shows different effect on HCE degradation.The HCE degradation enhances with the decrease of channel width in bulk nMOSFETs while the HCE degradation reduces with the decrease of channel length in SOI nMOSFETs.The effect of interface traps on HCE is discussed in order to discover the main physical mechanism. Meanwhile,the effect of border electric field distribution on HCE is discussed so as to explain the underlaid mechanism.The result can be a guide in making a choice of the device size and layout in IC design in practical deep submicron technology.

  Design and implementation of system sleep and wake up for embedded system based on S3C6410         

  SONG Li hua, ZHAN Ying, JIAN Yang, ZHANG Xin lei, BAO Shi kun

  2014, 36(05): 790-796. doi:

  Abstract ( 119 )   PDF (823KB) ( 282 )   　　

  As one of the key technologies of power management, system sleep and wake up realizes processor power mode switching and indirect device power management. The paper studies and realizes the sleep and wake up strategy based on S3C6410 and Windows Embedded CE 6.0 driver structure for an embedded system.Besides, many key issues,such as how to set up the wake up source,are analyzed.At last, the functional verification and performance analysis are carried out.Experimental results exhibit that our solution has high reusability and high stability.Without loss of generality,the proposed method can be referenced for other embedded system as a power control solution.

  论文

  Design and implementation of a SIMD
  floating-point divider based on SRT-8       

  DENG Ziye,CHEN Shuming,PENG Yuanxi,LEI Yuanwu

  2014, 36(05): 797-803. doi:

  Abstract ( 224 )   PDF (1088KB) ( 259 )   　　

  In the area of scientific computing, digital signal processing, communication and image processing, division is one of the widely used basic operations. Based on SRT-8 algorithm, a SIMD floating-point divider is designed,which is compatible to IEEE-754 standard.The divider supports one double precision floating point division and two parallel single precision floating point division on the same hardware platform.It reduces the iterative division calculation time delay and improves the frequency by optimizing the SRT8 iterative division structure,choosing parallel processing of quotient and residue addition,and adopting rapid storage technique. Besides,it reduces hardware resources and saves area by adopting reuse strategy.Experiments show that the synthesized cell area is 18 601.968 1μm2 and the frequency reaches up to 2.5GHz with 40nm technology library,and the latency of operation is reduced by 23.81％ in comparison to the traditional implementation based on SRT-8.

  MuxOS：A multiplex operating systems
  architecture for smart device    

  HAN Wei1，CHEN Yu1，LIU Yingli2，ZHANG Jiufeng3

  2014, 36(05): 804-808. doi:

  Abstract ( 152 )   PDF (686KB) ( 248 )   　　

  In order to reduce the performance overhead induced by virtualization for smart devices, MuxOS is proposed and realized. It is a system architecture to support multiple operating systems for smart devices.It is able to coordinate the execution of multiple Linuxbased Operating Systems independently on a single smart device.The work principle of MuxOS is introduced,and the running process is described.Test results show that MuxOS outperforms other virtualization products like Xen and allows switching operating systems under one second.

  Research of LARED-P on Intel Xeon Phi            

  YAO Wenke1，DU Yunfei2,WU Qiang1,YANG Canqun1

  2014, 36(05): 809-813. doi:

  Abstract ( 140 )   PDF (839KB) ( 225 )   　　

  Plasma simulations have been widely used to exploit scientific problems under extremely situations. The paper ports a particleincell based plasma code, LAREDP, to Intel Xeon Phi coprocessor. In order to accomplish this, two modes are employed, i.e. the Native mode and the Offload mode. Firstly, the Native mode is employed to study on the hot computing tasks, which have been accelerated to 4.61 times faster by using SIMD extension instructions. Secondly, the Offload mode is employed to transplant the whole code onto a CPUIntel Xeon Phi heterogeneous system. We also adopt optimizations such as asynchronous data transferring and double buffer technique to improve the performance. And we obtain 9.8% and 21.8% improvement respectively.
      

  Structure design of test pattern generator
  based on multiconfigurable LFSR

  LI Peng,YAN Xuelong,SUN Yuan

  2014, 36(05): 814-820. doi:

  Abstract ( 120 )   PDF (832KB) ( 249 )   　　

  In Built-In Self-Test (BIST), the fault coverage of traditional test generation is too low, and the hardware overhead is too large. To tackle these disadvantages, a multi-configurable LFSR structure of hybrid test vector generation is proposed. In the structure, matrix theory is used to configure the feedback network for random vectors and deterministic vectors. For the deterministic vector generation, an optimization algorithm of feedback configuration solution is proposed so as to reduce hardware overhead. The hybrid test vectors generated by the structure can ensure the test fault coverage, which can detect random pattern detectable faults and random pattern resistant faults in circuit under test. At last, some examples and several synthesized reference circuits are used to verify the feasibility of our proposal.

  Multi-core transaction level modeling and
  multi-view co-verification environment            

  WANG Jun，LIU Lei，ZHANG Long，LI Sikun

  2014, 36(05): 821-827. doi:

  Abstract ( 120 )   PDF (1213KB) ( 209 )   　　

  With the continuous rapid development of integrated circuit technology, the exponential growing of the number of onchip processor cores, the growing complexity of the design, the processor verification faces challenges. However, so far effective tools are still lacked. The paper proposes a multiview coverification method regarding transactionlevel modeling of multicore processors. Using a unified platform, the multiview coverification environment contains simulation verification, formal verification and application verification as three different views. Hence, multicore processors transactionlevel model validation task can be done in this integrated verification environment, owning multiple methods advantages of three different views. Based on a transactionlevel modeling and simulation platform, named SoCLib, we implement a good scalable multiview coverification environment called MVIE. Experimental results show that, compared with traditional single view verification, the proposed multiview coverification method has obvious advantages in transaction verification, especially in terms of convenience, completeness, efficiency, and model data consistency maintenance, etc.

  Design and implementation of TSV
  chain redundancy repair circuit in 3D chip                

  YUAN Qiang，ZHAO Zhenyu，DOU Qiang，LI Peng，LIU Haibin

  2014, 36(05): 828-835. doi:

  Abstract ( 186 )   PDF (1613KB) ( 236 )   　　

  The ThreeDimensional (3D) chip structure is becoming one of the most popular academic research fields in VLSI owing to its advantages such as high integration density, high frequency, lower power, and so on. TSV is the key technology for vertical interconnections in 3D chips. However, TSVs may have some faults during the TSV fabrication or the process of wafer thinning and bonding, which causes that the modules related TSV lose efficacy, even the entire chip doesn’t work normally. A singleredundancy and dualredundancy repair circuit based on TSV chain is proposed. The signals produced by chip testing are used to control repair circuit for the purpose of repairing the TSV defects and transferring the signals of fault TSV to the neighboring good TSV. The experimental results show that the function of this circuit structure is correct and the overall repair ratio can reach more than 91.97%, meanwhile the area overhead is lower.

  A flexible mandatory integrity access control policy               

  XU Feng1,WEI Lifeng2,ZHANG Guoyin1

  2014, 36(05): 836-841. doi:

  Abstract ( 122 )   PDF (519KB) ( 243 )   　　

  Integrity protection is an important content of computer security. Most of security OSes supported integrity protection mechanism, but integrity also may be destructed, and the protection mechanism is not flexible enough. Based on the principle of integrity protection, FIC (Flexible Integrity Control) policy is proposed and implemented under LSM (Linux Security Module). Integrity level and integrity auxiliary level is defined, FIC defines many rules including access control rules, process relabel rules and new objects labeled rules, FIC policy can protect system's integrity and process execution's flexible integrity protection. Implementation effect is analyzed, scalable requirement is pointed out.
      

  Optimization-variable fault-tolerant
  three-dimensional topology control            

  WANG Dong，DENG Hao

  2014, 36(05): 842-848. doi:

  Abstract ( 102 )   PDF (796KB) ( 217 )   　　

  In order to satisfy the requirements of connectivity,energy conservation,low interference and fault-tolerant preferences of wireless ad hoc network,topology control is an effective method.In the real world, the environment of ad hoc network communication is complicated,and the objective of network optimization may also change accordingly.In our research,a fault-tolerant threedimensional topology control algorithm is proposed.Its optimization objective is changeable. Under the premise of fault tolerance,it can minimize the interference when the influence by the interference is notable,but pay more attention on the energy conservation when the influence is slight.

  Detecting applications’malicious behaviors
  using Android system mechanism                

  WU Junchang1,LUO Shengmei2,WU Yan2,CHENG Shaoyin1,JIANG Fan1

  2014, 36(05): 849-855. doi:

  Abstract ( 191 )   PDF (624KB) ( 267 )   　　

  Android applications can use many mechanisms provided by Android system.But the improper use of these mechanisms may make catastrophe to user’s security and benefits. The paper proposes a program analysis method,which detects malicious behaviors in the mechanism. According to the characteristics of function, the corresponding function summary is constructed.The instruction level simulation is used to construct function summary,while the function level simulation is used to detect malicious behaviors. Based on the method above,a prototype system is designed and implemented.We use the system to detect a public malicious application sample library,and the results show that our method is effective.

  Attacks and improvement of two
  self-certified signcryption schemes

  WANG Yun

  2014, 36(05): 856-859. doi:

  Abstract ( 99 )   PDF (361KB) ( 239 )   　　

  Integrating the selfcertified public key technique and signcryption system enables both digital signature and encryption simultaneously in a fitted logical procedure and eliminates the certificate management problem and the key escrow problem. It has lower computational cost and saves the storage space, so it is important for us to construct secure and efficient self certified signcryption schemes. Analysis of Yu’s and Wang’s papers shows that they are not secure.The third can forge signature instead of the true signer with a pair of clear text and cipher text. We improve their schemes by rooting a random number in the digital signature scheme.Our improvement overcomes their disadvantage and achieves a higher security.
        

  Study and implementation of packet classification algorithms for OpenFlow                 

  Lv Zhao, LI Tao

  2014, 36(05): 860-865. doi:

  Abstract ( 146 )   PDF (588KB) ( 221 )   　　

  With the emergence of software defined network and OpenFlow in recent years, fine grained flow control based on the multi tuple packet classification makes a huge challenge to the traditional 5 tuple packet classification. The basic concept of packet classification, some typical packet classification algorithms and the packet classification for OpenFlow are introduced. For the demand of exact match in the OpenFlow packet classification, a counting and linked list Bloom Filter base on Hash, named OF_CBF, is designed and implemented. And it is tested and analyzed. For the demand of wildcard match in the OpenFlow packet classification, an algorithm based on finite state machine, named OF_FSMP is designed, implemented, tested and analyzed.
       

  论文

  Lowvoltage power line communication routing method
  based on spanning tree in graph theory        

  LI Xiang1，LIU Hongli1，LIU Shugang1,2，GU Zhiru1，CHEN Yan1

  2014, 36(05): 866-873. doi:

  Abstract ( 159 )   PDF (1121KB) ( 238 )   　　

  Due to the impedance characteristics, signal attenuation characteristics and noise characteristics of Power Line Channel (PLC), the reliability of the PLC becomes the important factor of restricting its wide application. The physical topology structure and the logical topology structure of low voltage distribution network are analyzed. According to the engineering characteristics of our country's lowvoltage concentrated meter reading system application, a PLC automatic routing method based on spanning tree in graph theory is proposed. The method can effectively construct power line communication network routes, and dynamically maintain the routes in accordance with the variation of channel, thus ensuring the reliability of power line network. The experimental test proves the validity, reliability and practicability of this routing method.
      

  A RFID secure authentication protocol based on RBAC              

  WANG Guichao,WANG Yan,LI Yongzhen

  2014, 36(05): 874-878. doi:

  Abstract ( 113 )   PDF (788KB) ( 245 )   　　

  For the low-cost RFID systems, the security and privacy problems are always the research hot spot. In order to protect the users’privacy, the existing security protocols mainly use the Hash function or traditional encryption algorithms to ensure the safety of the tag’s information. Although, to some extent, they guarantee the security of the information, all of them are nothing but ignore protecting the unauthorized tag’s information. For the sake of filling in the gap, a RFID secure authentication protocol based on RBAC is proposed. Through introducing the RBAC mechanism, our proposal can effectively not only ensure the security of the unauthorized tag’s information but also resist the reply attack, the internal reader attack, etc. Besides, using the partial ID and bit operation can reduce the system hardware requirements for the tag so that the proposed protocol is more suitable for low-cost RFID systems.
     

  Study for AHP-based access strategy
  in distributed constellation network            

  PAN Chengsheng，CHEN Zhiqiang，QIU Shaoming，SUI Lei

  2014, 36(05): 879-883. doi:

  Abstract ( 107 )   PDF (490KB) ( 200 )   　　

  The distributed constellation network is a powerful weapon to win the future information warfare.  The access strategy is of great significance in distributed constellation network for promoting the ability to obtain aerospace information. An access strategy based on the Analytic Hierarchy Process (AHP) is proposed for the characteristics of the distributed constellation network,such as high dynamic topology and easily load utilization of satellite resources imbalances.Firstly,the weights of various indicators for the resource utilization rate are dynamically calculated using the analytic hierarchy process. Secondly,the resource utilization rate is dynamically adjusted according to the real time resources status of each satellite node.The simulation results demonstrate that the new call blocking rate and the forced discontinuity rate can be reduced by using the proposed strategy,thus solving the load balancing problem effectively and improving the allocation rationality of the group business in the distributed constellation network.
        

  Research on the compliance testing of CNONIX standard          

  WU Jieming,LI Shuozheng

  2014, 36(05): 884-890. doi:

  Abstract ( 122 )   PDF (600KB) ( 244 )   　　

  CNONIX (China Online Information Exchange) standard specifies the data and data format used in the procedure of online information exchange in the field of press and publication, which enhances the quality of the data and the efficiency of the exchanging procedure.To ensure that a thirdpart software can produce XML files under the CNONIX standard and check if an XML file conforms to the standard, a compliance testing method is proposed.Attributes of data in CNONIX standard are studied and their impact on test suite is analyzed.Then,a series of rules for testing the XML files are designed.At last, an application case is used to explain the testing flow.

  An approach of adjusting the probability
  of error statements based on testing results         

  WANG Zhenzhen

  2014, 36(05): 891-899. doi:

  Abstract ( 122 )   PDF (737KB) ( 211 )   　　

  Approaches for fault localization based on test suites are now collectively called TBFL (Testing Based Fault Localization). However, current algorithms do not take advantage of the prior knowledge about test cases and program so that they waste these valuable "resources". Stochastic TBFL is a new kind of TBFL approach whose spirit is to combine the prior knowledge with actual testing activities under stochastic theory, so as to locate program faults. Stochastic TBFL may be regarded as a general pattern of this approach, from which people can develop various algorithms. We separate the prior knowledge about program and test suites from actual testing activities, and according to testing results we then add the prior knowledge. This new method is called adjusting the probability of error statements based on testing results. Comparison to stochastic TBFL and some instances shows that our improved approach is feasible. Moreover, the paper proposes three standards for comparing different TBFL approaches. And from the investigation of the three standards, results of our proposed approach are also good.
        

  A runtime verification method for
  embedded operating system          

  ZHANG Kedi,SHU Shaoxian,DONG Wei

  2014, 36(05): 900-905. doi:

  Abstract ( 153 )   PDF (899KB) ( 307 )   　　

  As an effective supplement of testing and model checking, runtime verification technique attracts more and more attentions. However, the current runtime verification technology is mainly used for application software. Very few are specialized for monitoring the running state of an operating system. The paper studies the runtime verification framework and key techniques for embedded operating system and realizes a demo combined with an open source system FreeRTOS. Firstly, an embedded operating system oriented framework for runtime verification and feedback adjustment is proposed. Secondly, based on the critical part of our frame, the specification language, threevalued semantic monitor generation and FreeRTOS related interfaces are designed and implemented.