关键词: 异步, 流水线结构优化, 操作数检测, 低功耗, 乘法器

Abstract:

The asynchronous logic only performs actions on demand, and it is often adopted in the powerefficient design. There are three significant factors that may affect the power consumption of pipelined circuits: the structure of the pipeline, the behavior of the operation, and characteristics of operands. In this paper, the three factors are analyzed, and a poweroptimized desynchronized multiplier considering the influence of the factors is designed. The experiments show that the proposed multiplier has lower power dissipation and higher performance than the traditional desynchronized multipliers.

Key words: asynchronous;pipeline structure optimization;operand detecting;low power;multiplier