• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2012, Vol. 34 ›› Issue (7): 65-70.

• 论文 • 上一篇    下一篇

“腾越II”嵌入式异步微处理器的设计与实现

苏博,石伟,王志英,任洪广,王友瑞   

  1. (国防科学技术大学计算机学院,湖南 长沙 410073)
  • 收稿日期:2010-05-28 修回日期:2010-09-06 出版日期:2012-07-25 发布日期:2012-07-25
  • 基金资助:

    国家863计划资助项目(2007AA01Z101);国家自然科学基金资助项目(60873015)

Design and Implementation of an Asynchronous Embedded Processor:TengYueⅡ

SU Bo,SHI Wei,WANG Zhiying,REN Hongguang,WANG Yourui   

  1. (School of Computer Science,National University of Defense Technology,Changsha 410073,China)
  • Received:2010-05-28 Revised:2010-09-06 Online:2012-07-25 Published:2012-07-25

摘要:

嵌入式系统对处理器功耗开销有严格的限制,异步电路技术可以作为设计低功耗处理器的有效方法之一。针对嵌入式多媒体应用,本文设计实现了一款低功耗异步微处理器——腾越II。处理器中包含一个异步TTA微处理器内核、一个同步TTA微处理器内核、两个存储控制器和多个外部通信接口。异步内核通过基于宏单元的异步电路设计方法实现,其它部分通过基于标准单元的半定制设计流程实现。处理器芯片采用UMC 0.18μm CMOS工艺实现,基片面积为4.89×4.89mm2,工作电压为1.8V。经测试,处理器工作主频达到200MHz,且异步内核的功耗开销低于同步内核的50%。

关键词: 低功耗, 传输触发体系结构, 异步电路, 嵌入式多媒体应用

Abstract:

In embedded systems, the power consumption of processors is restricted to a low limit. Asynchronous circuit techniques can be effective methods to design low power processors. In order to meet the performance and power requirements of the multimedia applications in embedded systems, a low power asynchronous microprocessor named “TengYueⅡ”  is designed and implemented. A 32bit onchip bus, two transport triggered architecture cores, two memory controllers and several communication interfaces form the processor. One processor core is based on asynchronous circuits and the other one is its synchronous counterpart. TengYueⅡ processor is implemented in the UMC 0.18μm CMOS technology and the supply voltage is 1.8V. The area of the chip is 4.89mm×4.89mm. The experimental results show that both cores can run correctly at the frequency of 200MHz and the asynchronous core’s power consumption is lower than 50% of the synchronous core.

Key words: low power;transport triggered architecture;asynchronous circuit;embedded multimedia application