3D-SRAM中的TSV开路故障模型研究

J4 ›› 2014, Vol. 36 ›› Issue (12): 2331-2338.

3D-SRAM中的TSV开路故障模型研究

蒋剑锋，赵振宇，邓全，朱文峰，周康

（国防科学技术大学计算机学院，湖南长沙 410073）

收稿日期:2014-05-19 修回日期:2014-07-20 出版日期:2014-12-25 发布日期:2014-12-25

Research of TSV open defects in 3D SRAM

JIANG Jianfeng,ZHAO Zhenyu,DENG Quan,ZHU Wenfeng,ZHOU Kang

(College of Computer,National University of Defense Technology,Changsha 410073,China)

Received:2014-05-19 Revised:2014-07-20 Online:2014-12-25 Published:2014-12-25

摘要/Abstract

摘要：

基于3D-IC技术的3D SRAM，由于硅通孔TSV制造工艺尚未成熟，使得TSV容易出现开路故障。而现有的TSV测试方式均需要通过特定的电路来实现，增加了额外的面积开销。通过对2D Memory BIST的研究，针对3D SRAM中的TSV全开路故障进行建模，根据TSV之间的耦合效应进行广泛的模拟研究，分析并验证在读写操作下由于TSV的开路故障对SRAM存储单元里所存值的影响，将TSV开路故障所引起的物理故障映射为SRAM的功能故障。该故障模型可以在不增加额外测试电路的情况下，为有效测试和解决这种TSV开路故障提供基础。

关键词: 3D-IC, TSV, 开路故障, 测试, 建模

Abstract:

In 3D SRAM based on 3DIC technology,the manufacturing process of TSV is not mature yet,thus making TSVs be prone to open defects.And the existing test methods of TSV require a specific circuit, which increases the area overhead. Derived from 2D Memory BIST,the faulty behaviors (full open defects) of TSV in 3D SRAM are modeled.Based on coupling effects between TSVs we study the behaviors of SRAM cell through simulations, analyze and verify the influence of open defects on the existing values of SRAM cells in read and write operations.The physical faults caused by TSV open defects are mapped into SRAM functional faults.It is an effective method for testing and solving the open defects of TSVs without introducing any additional testing circuit in this way.

Key words: 3D-IC;TSV;open defects;test;model

蒋剑锋，赵振宇，邓全，朱文峰，周康. 3D-SRAM中的TSV开路故障模型研究[J]. J4, 2014, 36(12): 2331-2338.

JIANG Jianfeng,ZHAO Zhenyu,DENG Quan,ZHU Wenfeng,ZHOU Kang. Research of TSV open defects in 3D SRAM [J]. J4, 2014, 36(12): 2331-2338.

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