关键词: SystemVerilog断言, 测试生成, Surrogate模型

Abstract: As the scale of integrated circuit design continues to increase, verification has become one of the bottlenecks in the design process. Currently, simulation is still one of the dominant methods for integrated circuit design verification, and the completeness of simulation is usually measured by various coverage metrics. Functional coverage is a higher level of coverage, and in practical engineering, functions are often presented in the form of SystemVerilog assertions. Currently, it is difficult to generate a large number of test vectors that activate assertions using commonly used random test vector generation methods. When using constraint solving strategies, if the coverage condition involves non-initial input signals (internal signals, output signals), the efficiency of constraint solving will be extremely low, making it still difficult to cover the target assertion. To address the coverage problem of assertions containing non-initial input signals, this paper proposes a Surrogate model-based assertion coverage improvement method, which mainly generates a Surrogate model that reflects the relationship between non-initial input signals and initial input signals and only contains initial input signals, and then uses this Surrogate model as the object of constraint solving, thus reducing the complexity of constraint solving. Experimental results show that this method has a significant improvement in assertion coverage compared to random test vector generation.

Key words: SystemVerilog assertion, test generation, Surrogate model