基于改进CAF-WAS的绑定前硅通孔测试

计算机工程与科学

基于改进CAF-WAS的绑定前硅通孔测试

卞景昌1，梁华国1,2，聂牧2，倪天明1，徐秀敏1，黄正峰1

（1.合肥工业大学电子科学与应用物理学院,安徽合肥 230009;2.合肥工业大学计算机与信息学院，安徽合肥 230009）

收稿日期:2016-09-06 修回日期:2016-11-18 出版日期:2017-03-25 发布日期:2017-03-25
基金资助:
国家自然科学基金（61674048,61574052,61371025,61474036）

CAF-WAS based pre-bonding TSV testing

BIAN Jing-chang1,LIANG Hua-guo1,2,NIE Mu2,NI Tian-ming1,XU Xiu-min1,HUANG Zheng-feng1

(1.School of Electronic Science & Applied Physics,Hefei University of Technology,Hefei 230009;

2.School of Computer & Information,Hefei University of Technology,Hefei 230009,China)

Received:2016-09-06 Revised:2016-11-18 Online:2017-03-25 Published:2017-03-25

摘要/Abstract

摘要：

硅通孔TSV发生开路故障和泄漏故障会降低三维集成电路的可靠性和良率，因此对绑定前的TSV测试尤为重要。现有CAF-WAS测试方法对泄漏故障的测试优于其他方法(环形振荡器等)，缺点是该方法不能测试开路故障。伪泄漏路径思想的提出，解决了现有CAF-WAS方法不能对开路故障进行测试的问题。另外，重新设计了等待时间产生电路，降低了测试时间开销。HSPICE仿真结果显示，该方法能准确预测开路和泄漏故障的范围，测试时间开销仅为现有同类方法的25%。

关键词: 三维集成电路, 硅通孔(TSV), 自测试, 伪泄漏路径, 开路故障

Abstract:

Though silicon via (TSV) open/leakage defect reduces the reliability and yield of three-dimensional integrated circuits, so pre-bonding TSV tests are especially important. The existing charge and float, wait and sample (CAF-WAS) test method for leakage defect test is superior to other methods such as ring oscillator, etc., however, it cannot test open defect. We propose a pseudo leak path thought to solve this problem. In addition, we redesign a waiting time generation circuit of to reduce the test time overhead. HSPICE simulation results show that the proposed method can accurately forecast the open defect and the scope of the leakage defect with only 25% test time of the existing method ［14］.

Key words: three-dimensional integrated circuits, TSV, self-test, false leakage path, open defect

卞景昌, 梁华国, 聂牧, 倪天明, 徐秀敏, 黄正峰. 基于改进CAF-WAS的绑定前硅通孔测试[J]. 计算机工程与科学.

BIAN Jing-chang, LIANG Hua-guo, NIE Mu, NI Tian-ming, XU Xiu-min, HUANG Zheng-feng. CAF-WAS based pre-bonding TSV testing[J]. Computer Engineering & Science.

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[7]	陈明静[1] 向东[2]. 基于扫描森林的BIST策略[J]. J4, 2005, 27(4): 36-39.
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[9]	陈火军江建慧. VLSI电路短路和开路故障模型研究进展[J]. J4, 2005, 27(4): 49-53.