一种面向三维众核微处理器的新型NoC拓扑结构

摘要/Abstract

摘要：

三维微处理器具有集成度高、全局互连线短及连接部件多的优势，但是传统的三维拓扑结构在大规模系统中无法充分利用垂直方向上低延时高带宽的特性，很难满足大规模众核微处理器低直径、高带宽、高扩展性的需求。针对三维NoC网络直径大、可扩展性要求高以及路由端口多的问题，提出了一种基于多级垂直域的三维拓扑结构—V-Spidergon，其在水平层上采用Spidergon结构，在垂直方向上采用多级垂直域扩展结构，域内及域间均实现全互连。实验数据表明，在8层、16层和32层堆叠下，V-Spidergon结构的延时较3D-Mesh分别降低15.1%、28.5%和55.7%，较NoC-Bus分别降低11.5%、32.7%和77.6%；在15%和100%负载率注入情形下，V-Spidergon的平均延时表现出与水平层数增加不相关的特性。

关键词: 众核微处理器, 片上网络, 三维集成电路, 3D-Mesh, NoC-Bus, 多级垂直域结构

Abstract:

3D microprocessors have advantages of high-level integration, short global interconnection and more connecting parts. However the traditional 3D topology cannot take full advantage of the characteristics of 3D integrated circuits in the vertical direction. It is difficult for these structures to meet the requirements of large-scale many-core processors, such as short diameter, high-bandwidth and highly scalability. We propose a 3D on-chip interconnection network topology, called V-Spidergon. In the horizontal layer, the V-Spidergon adopts the Spidergon topology in the horizontal layer and a domain-based interconnected structure in the vertically direction. The entire vertical network is divided into multi-level domains according to the hierarchical domain thought, and every domain interconnects with each other. Simulation results show that the time delays in 8 layers, 16 layers and 32 layers of the V-Spidergon are lower than those of the 3D-Mesh by 15.1%, 28.5%, 55.7% respectively, and are also lower than those of the NoC-Bus by 11.5% 32.7% and 77.6% respectively; under injections of 15% and 100% load rates, the average time delay of the V-Spidergon does not increase with the growth of horizontal layers.

Key words: many-core microprocessor, network on chip, 3D integrated circuit, 3D-Mesh, NoC-Bus, hierarchical vertical domain

陈继承，王洪伟，张闯. 一种面向三维众核微处理器的新型NoC拓扑结构[J]. 计算机工程与科学.

CHEN Ji-cheng,WANG Hong-wei,ZHANG Chuang. A novel NoC topology for 3D many-core microprocessors [J]. Computer Engineering & Science.

参考文献

［1］Hoefflinger B. ITRS: The international technology roadmap for semiconductors［M］∥Chips 2020. Berlin:Springer Berlin Heidelberg,2012: 161-174.
［2］Lim S K. 3D-MAPS: 3D massively parallel processor with stacked memory［M］∥Design for High Performance,Low Power,and Reliable 3D Integrated Circuits.New York:Springer Science+Business Media,2013: 537-560.
［3］Sheibanyrad A,Petrot F,Jantsch A. 3D integration for NoC-based SoC architectures［M］. Springer,2011.
［4］Ahmed A B,Abdallah A B. Architecture and design of high-throughput,low-latency,and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)［J］. The Journal of Supercomputing,2013,66(3): 1507-1532.
［5］Kim J S,Oh C S,Lee H,et al. A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 128 I/Os using TSV based stacking［J］. IEEE Journal of Solid-State Circuits,2012,47(1): 107-116.
［6］Goel S K,Adham S,Wang M J,et al. Test and debug strategy for TSMC CoWoS? stacking process based heterogeneous 3D IC: A silicon case study［C］∥Proc of IEEE 2013 IEEE International Test Conference (ITC),2013: 1-10.
［7］Sibai F N,El-Moursy A,Mohamed N. Throughput and latency analysis of the Spidergon-Donut interconnection network［C］∥Proc of IEEE 2012 International Conference on Innovations in Information Technology (IIT),2012: 356-360.
［8］Cakir C,Ho R,Lexau J,et al. Modeling and design of high-radix on-chip crossbar switches［C］∥Proc of the 9th International Symposium on Networks-on-Chip,2015: 20.
［9］Rahmani A M,Liljeberg P,Latif K,et al. Congestion aware,fault tolerant,and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures［C］∥Proc of 2011 5th IEEE/ACM International Symposium on Networks on Chip (NoCS),2011: 65-72.
［10］Rahmani A M,Vaddina K R,Latif K,et al. Generic monitoring and management infrastructure for 3D NoC-Bus hybrid architectures［C］∥Proc of 2012 6th IEEE/ACM International Symposium on Networks on Chip (NoCS),2012: 177-184.
［11］Gu H, Wang S, Yang Y, et al. Design of butterfly-fat-tree optical network on -chip［J］. Optical Engineer,2010,49(9):095402-7.
［12］Rahmani A M,Liljeberg P,Plosila J,et al. An efficient hybridization scheme for stacked mesh 3D NoC architecture［C］∥Proc of 2012 20th Euromicro International Conference on Parallel,Distributed and Network-Based Processing (PDP),2012: 507-514.
［13］Rahmani A M,Liljeberg P,Plosila J,et al. Exploring a low-cost and power-efficient hybridization technique for 3D NoC-bus hybrid architecture using Last Z-based routing algorithms［J］. Journal of Low Power Electronics,2012,8(4): 403-414.
［14］Ben-Itzhak Y,Cidon I,Kolodny A. Delay analysis of wormhole based heterogeneous NoC［C］∥Proc of 2011 5th IEEE/ACM International Symposium on Networks on Chip (NoCS),2011: 161-168.
［15］Rahmani A M,Vaddina K R,Latif K,et al. High-performance and fault-tolerant 3D NoC-bus hybrid architecture using ARB-NET-based adaptive monitoring platform［J］. IEEE Transactions on Computers,2014,63(3): 734-747.
［16］Bishnoi R,Kumar P,Laxmi V,et al. Distributed adaptive routing for spidergon NoC［C］∥Proc of the 18th International Symposium on VLSI Design and Test,2014: 1-6.
［17］Shi S,Wang X,Xu C,et al. Simulation and fabrication of two Cu TSV electroplating methods for wafer-level 3D integrated circuits packaging［J］. Sensors and Actuators A Physical,2013,203(12): 52-61.
［18］Weldezion A Y,Grange M,Pamunuwa D,et al. A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns［C］∥Proc of 2013 IEEE International 3D Systems Integration Conference (3DIC),2013: 1-5.

[1]	高文才, 陈小文. 一种基于混合加固的容软错误NoC路由器[J]. 计算机工程与科学, 2023, 45(08): 1376-1382.
[2]	葛一漩, 李晨, 陈小文, 鲁建壮, 郭阳. 一种定制片上网络设计探索算法的设计与实现[J]. 计算机工程与科学, 2023, 45(06): 970-978.
[3]	康子扬, 彭凌辉, 周干, 林博, 王蕾. 一种用于片上网络的拥塞感知哈密尔顿最短路径路由算法[J]. 计算机工程与科学, 2022, 44(06): 986-993.
[4]	陈小帆, 杨智杰, 彭凌辉, 王世英, 周干, 李石明, 康子扬, 王耀, 石伟, 王蕾. 一种类脑处理器片上网络的验证框架[J]. 计算机工程与科学, 2022, 44(05): 769-778.
[5]	石伟, 龚锐, 刘威, 王蕾, 冯权友, 张剑锋. 面向高带宽I/O的片上网络优化[J]. 计算机工程与科学, 2021, 43(09): 1538-1545.
[6]	齐星云, 戴艺, 赖明澈, 常俊胜, 董德尊. 基于偏折路由的双环片上网络[J]. 计算机工程与科学, 2021, 43(03): 381-388.
[7]	吉慧，周磊. 面向温度优化的片上网络任务调度方法[J]. 计算机工程与科学, 2018, 40(09): 1527-1533.
[8]	卞景昌1，梁华国1,2，聂牧2，倪天明1，徐秀敏1，黄正峰1. 基于改进CAF-WAS的绑定前硅通孔测试[J]. 计算机工程与科学, 2017, 39(03): 430-435.
[9]	丁毓良，张剑贤，周端，裘雪红. 直线引导的Torus结构路由算法[J]. 计算机工程与科学, 2017, 39(02): 275-279.
[10]	宋国治，涂遥，张大坤，温越博. 一种用于片上网络布图规划的改进模拟退火与粒子群混合算法[J]. J4, 2016, 38(05): 863-870.
[11]	王玉，唐遇星，窦强. 一种支持Subcacheline结构的三维Cache模拟器的设计[J]. J4, 2013, 35(10): 154-158.
[12]	齐树波，李晋文，乐大珩，赵天磊，张民选. 一种面向片上互连的自适应通道双缓冲延迟模型[J]. J4, 2012, 34(9): 58-63.
[13]	朱幸辉,黄镜如. 片上网络路由算法分析与评估[J]. J4, 2012, 34(5): 63-67.
[14]	冯超超，张民选，蒋江，李晋文. 面向片上网络容错偏转路由器设计与优化[J]. J4, 2012, 34(2): 56-61.
[15]	师帅，窦文华，鲁佳. 基于二维Mesh结构片上网络的路由策略方法研究[J]. J4, 2011, 33(5): 32-37.