关键词: 高清视频编解码后处理, 卷积神经网络, 现场可编程逻辑门阵列, 硬件实现

Abstract:

Aiming at the shortcomings of the post-processing CNN algorithm running on the common platform according to the high-efficiency video code standard, we propose a postprocessing convolutional neural network hardware parallel architecture based on field programmable gate array (FPGA) to improve the overall parallelism of the convolution module and the hardware flow of the module by optimizing the concurrent data input and output buffering process. Experiments on 176×144 video streams on the Xilinx ZCU102 show that the proposed CNN hardware accelerator can achieve an equivalent computational performance of 360.5G floating-point operation per second. The computation speed can satisfy 81.01 FPS, which is 76.67 times faster than that of the Intel i7-4790K with a clock frequency of 4Ghz. The speedup is 32.50 times faster than the NVIDIA GeForce GTX 750Ti. In the calculation of energy efficiency ratio, the proposal’s power consumption is 12.095W, 512.9 times of that of the Intel i74790K and 125.78 times that of the NVIDIA GeForce GTX 750Ti.

Key words: HEVC post-processing, convolutional neural network, field programmable logic gate array(FPGA), hardware implementation