• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2013, Vol. 35 ›› Issue (7): 11-15.

• 论文 • 上一篇    下一篇

基于KILL规则的双通道3D众核NoC原型构建

谭海   

  1. (1.北京理工大学计算机学院,北京 100081;
    2.东华理工大学信息工程学院,江西 南昌 330013)
  • 收稿日期:2012-05-23 修回日期:2012-09-06 出版日期:2013-07-25 发布日期:2013-07-25
  • 基金资助:

    国家自然科学基金资助项目(60973010);高等学校博士学科点专项科研基金资助项目(200800071005,20070007070);江西省自然科学基金资助项目(20114BAB201024);江西省教育厅科技项目(GJJ11493);核技术应用教育部工程研究中心开放基金资助项目(HJSJYB201011);东华理工大学校长基金项目(DHXK0935)

Prototype construction of a dual-channel
3D many-core NoC based on KILL rule

TAN Hai1,2   

  1.  (1.School of Computer,Beijing Institute of Technology,Beijing 100081;
    2.School of Information Engineering,East China Institute of Technology,Nanchang 330013,China)
  • Received:2012-05-23 Revised:2012-09-06 Online:2013-07-25 Published:2013-07-25

摘要:

为设计一个低开销低时延的众核NoC系统,提出了一种使用3D叠片技术的双通道片上众核体系AUTSDN,应用KILL规则确定了片上众核中组内处理核的个数,并基于MIT的Graphite模拟器建立了该体系的原型。AUTSDN体系中采用3D叠片分组多级片上互连网络,并且根据通信内容的不同,控制信号和数据信号的传输采取不同的通信链路。原型系统中的模拟测试结果表明,相比传统的2D片上网络,功耗降低了20%,时延降低了30%,同时AUTSDN的系统层次化特征确保了良好的系统扩展性。

关键词: 3D叠片, 众核原型, 低功耗, 低时延, 双通道

Abstract:

In order to design a lowdelay and lowoverhead manycore NetworkonChip (NoC), the paper proposes an Architecture Utilizing 3D Stack Hierarchical Dualchannel NoC (AUSHDN) and KILL(Kill If Less Linear)rule is used to determine the number of processing cores in each group of AUSHDN. What's more, the prototype of the AUSHDN system is established based on the Graphite simulator from MIT. In AUSGHN system, 3D stack Hierarchical multilevel internetonchip is employed and different communication link is used to transfer control and data signal according to different content of communication. The results of simulation test in prototype system show that: compared with the traditional 2D NOC, the power consumption has reduced by 20% and the time delay has shortened by 30%. Meanwhile, the hierarchy feature of the AUSGHN system guarantees its good scalability.

Key words: 3D stack;manycore prototype;lowpower;lowdelay;dualchannel