Abstract:

With the progress of semiconductor manufacturing techniques and the development of processor architectures, the gap between the processor and the DRAM speeds is becoming larger and larger, and memory bandwidth is now the primary bottleneck of improving the computer system performance. Modern DRAM provides several independent memory banks, according to this characteristics, we present a virtual channel based memory access scheduler, and a least wait time and readfirst scheduling approach. This approach significantly reduce the observed main memory access latency and improve the effective memory bandwidth utility.

Key words: memory access scheduling;virtual channel;SDRAM memory system;memory bandwidth