Abstract:

Interpretationbased instruction set emulation provides a solution to the binary compatibility problem. The organization of the interpretation process has great impact on the performance of an interpreter. Centralized interpretation is inefficient while the traditional threaded interpretation is not suitable for interpreting the CISC Instruction Set Architecture (ISA) because of the complicated instruction decoding process. We propose a DICachebased hybrid interpretation technique. DICache can dynamically predecode the source instruction and convert them into an intermediate form. The DICache access code is appended at the end of each interpreter routine, which enables the threaded interpretation for CISC ISA. We implement an interpreter which interprets the IA32 instructions on VLIW. We conduct some benchmarks from SPEC INT 2000 to evaluate the performance of the novel threaded interpretation method. It is demonstrated that DICachebased hybrid threaded interpretation can significantly improve the performance of an interpreter.

Key words: binary compatibility;instruction set emulation;threaded interpretation;DICache