• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2012, Vol. 34 ›› Issue (7): 54-59.

• 论文 • Previous Articles     Next Articles

Runtime Partitioning Technique of Hybrid Distributed Shared Memory Space in Multicore Processors

CHEN Xiaowen1,CHEN Shuming1,LU Zhonghai2,Axel Jantsch2   

  1. 1.School of Computer Science,National University of Defense Technology,Changsha 410073,China;
    2.Department of Electronic Systems,KTHRoyal Institute of Technology,Stockholm 16440,Sweden)
  • Received:2010-07-05 Revised:2010-10-24 Online:2012-07-25 Published:2012-07-25

Abstract:

In multicore processors, Distributed Shared Memory (DSM) offers ease of programming by maintaining a global virtual memory space as well as imports the inherent overhead of translating virtual memory addresses into physical memory addresses, resulting in negative performance. We observe that, in parallel applications, different data have different properties (private or shared). Even for the same datum, its property may be changeable in different phases of the program execution. This paper firstly introduces a hybrid DSM, aiming at supporting fast and physical memory accesses for private data and maintaining a global and single virtual memory space for shared data. A runtime partitioning technique is proposed to change the hybrid DSM organization during the program execution. It ensures fast physical memory addressing on private data and conventional virtual memory addressing on shared data, improving the performance of the entire system by reducing virtualtophysical address translation overhead as much as possible. The experimental results show that the hybrid DSM with runtime partitioning demonstrates performance advantage over the conventional DSM counterpart. The percentage of performance improvement depends on network size, problem size, way of data partitioning, etc. In our experiments, the maximal improvement is 13.14%, and the minimal improvement 6.98%.

Key words: address translation;data property;runtime partitioning;distributed shared memory;multicore processor