Abstract:

Dual-clock FirstInput First-Out (FIFO) structure is very useful for transferring data between modules operating in different clock domains. As more and more independent clock domains are integrated onto a SystemonaChip (SoC), the traditional dualclock FIFO structure increases the design complexity of clock networks, thus blocking the increase of the chip size and the frequency. The paper proposed a distributedcontrolled dualclock FIFO structure. The proposal uses the technology of sourcesynchronous data transfer so as to avoid the design complexity of clock networks, which is induced by distributing the sender's clock into the receiver's clock domain. The paper implemented this design and further introduced its optimization according to the performance and the realizability.

Key words: dualclock FIFO； distributed controlled； source synchronous data transfer； synchronizer； Gray code