Abstract:

Through Silicon Via (TSV) based ThreeDimensional Integrated Circuit (3DIC) introduces TSV into Power Distribution Network (PDN), and silicon substrate effect cannot be ignored because of 3D stack. Therefore, modeling PDN in TSVbased 3DIC must take TSV and silicon substrate effect into consideration. A model for 3D PDN in TSVbased 3DIC with silicon substrate effect is proposed. The proposed model is composed of a P/G (Power/Ground) TSV pair model and an onchip PDN model. In the modeling procedure of 3D PDN, the P/G TSV pair model with a bump and a contact is proposed based on a proved model, which reflects the electronic characteristics of P/G TSV pairs better. Additionally, the onchip PDN model, introducing the silicon substrate effect by conformal mapping method,is proposed based on the model proposed by Pak J S,which can reflect the silicon substrate effect on the electronic characteristics of PDN more effectively.The proposed model of 3D PDN is validated by experiments to prove that the proposed model of 3D PDN can evaluate the PDN impedance well and fast.

Key words: 3D-IC;PDN;P/G TSV;PDN impedance;silicon substrate effect