| [1] |
LU Xicheng, YANG Bo, LIU Jie, HUANG Libo, CHEN Xinhai.
Discussion on the development of HPC-AI converged high performance computing technologies
[J]. Computer Engineering & Science, 2026, 48(4): 571-579.
|
| [2] |
GENG Huantong, FAN Zichen, JIANG Jun, LIU Zhenyu, LI Jiaxing.
An end-to-end visual multi-task learning model for task prompts fusion
[J]. Computer Engineering & Science, 2026, 48(3): 456-466.
|
| [3] |
SHI Yongzhen1, 2, MO Haotian1, 2, HU Xingyu1, 2, LIU Jie1, 2, WANG Qinglin1, 2.
Optimization of ILU decomposition parallel algorithm on MIMD many-core architecture
[J]. Computer Engineering & Science, 2025, 47(9): 1544-1554.
|
| [4] |
CHENG Qihong1, LIU Peng1, YAO Lian1, YOU Zhiqiang2, WU Jigang1.
A fault tolerance scheme for memristive neural network under stuck-at faults
[J]. Computer Engineering & Science, 2025, 47(9): 1691-1699.
|
| [5] |
MING Tianbo1, LIU Biwei1, 2, HU Chunmei1, 2, WU Zhenyu1, 2, SONG Ruiqiang1, 2, SONG Fangfang1.
An automated physical compiler for multi-port register files
[J]. Computer Engineering & Science, 2025, 47(6): 976-987.
|
| [6] |
YANG Qianming, SHAO Jingjie, ZENG Pin, YUAN Meng, SONG Zhuoqin, DENG Qiuyan, ZHANG Jianfeng, WANG Yong.
Design and implementation of a distributed shared buffer switch based on Crossbar structure
[J]. Computer Engineering & Science, 2025, 47(6): 951-957.
|
| [7] |
XIE Yang, LI Chen, CHEN Xiaowen.
A near-data processing architecture for data-intensive applications
[J]. Computer Engineering & Science, 2025, 47(5): 797-810.
|
| [8] |
HONG Wentao, WU Lizhou, ZHANG Jintao, MENG Fanfeng, OU Yang, WANG Zicong, XIAO Nong .
A survey of memory pool systems based on emerging memory-semantic interconnect protocols
[J]. Computer Engineering & Science, 2025, 47(4): 601-611.
|
| [9] |
LI Hua, WANG Yongwen.
Does the ISA really matter?—A survey of simulations based on Gem5
[J]. Computer Engineering & Science, 2025, 47(11): 1945-1952.
|
| [10] |
HU Jintao, XU Xuezheng, YANG Deheng, HUANG Anwen, KOU Guang, LI Qiong.
An efficient method for RISC-V memory consistency testing based on loop unrolling
[J]. Computer Engineering & Science, 2025, 47(11): 1932-1944.
|
| [11] |
ZHANG Jia-hao, DENG Jin-yi, YIN Shou-yi, WEI Shao-jun, HU Yang.
Exploration of the many-core data flow hardware architecture based on Actor model
[J]. Computer Engineering & Science, 2024, 46(6): 959-967.
|
| [12] |
WEI Yi, YANG Zhi-jie, TIE Jun-bo, SHI Wei, ZHOU Li, WANG Yao, WANG Lei, XU Wei-xia.
A multistage dynamic branch predictor based on Hummingbird E203
[J]. Computer Engineering & Science, 2024, 46(5): 785-793.
|
| [13] |
LIU Zhong, LI Cheng, TIAN Xi, LIU Sheng, DENG Rang-yu, QIAN Cheng-dong.
MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors
[J]. Computer Engineering & Science, 2024, 46(2): 191-199.
|
| [14] |
WANG Qiang, SUN Yan-jie, QI Xing-yun, XU Jia-qing.
Bowtie 2-NUMA: Gene sequence alignment application with NUMA architecture adaptability
[J]. Computer Engineering & Science, 2024, 46(12): 2117-2127.
|
| [15] |
CHEN Xiao-wen, RUI Zhi-chao, ZHU Qi-jin, DONG Yu, MENG Yu, .
Design and FPGA implementation of a high-precision double step branching hybrid CORDIC algorithm
[J]. Computer Engineering & Science, 2024, 46(12): 2099-2108.
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