[1] |
WANG Jie, FU Dan-yang, .
ROB compression method based on RISC-V superscalar processor
[J]. Computer Engineering & Science, 2024, 46(07): 1185-1192.
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[2] |
WEI Yi, YANG Zhi-jie, TIE Jun-bo, SHI Wei, ZHOU Li, WANG Yao, WANG Lei, XU Wei-xia.
A multistage dynamic branch predictor based on Hummingbird E203
[J]. Computer Engineering & Science, 2024, 46(05): 785-793.
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[3] |
ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
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[4] |
LI Fei, GUO Shao-zhong, ZHOU Bei, SONG Guang-hui, HAO Jiang-wei, XU Jin-chen.
Performance optimization of RISC-V basic math library
[J]. Computer Engineering & Science, 2023, 45(09): 1532-1543.
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[5] |
SUN Cai-xia, SUI Bing-cai, DENG Quan, ZHENG Zhong, NI Xiao-qiang, WANG Yong-wen.
A hybrid ISA processor compatible with RISC-V at application level
[J]. Computer Engineering & Science, 2023, 45(08): 1347-1353.
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[6] |
MU Ming-ren, JIA Hai-peng, ZHANG Yun-quan, DENG Ming-sen, QU Guo-yuan, WEI Da-zhou, ZHANG Guang-ting.
Optimization of median filtering algorithm based on ARM architecture
[J]. Computer Engineering & Science, 2022, 44(10): 1738-1746.
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[7] |
LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
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[8] |
GU Yue, ZHAO Yin-liang.
Implementation and optimization of sparse matrix vector multiplication based on RISC-V vector instruction
[J]. Computer Engineering & Science, 2022, 44(01): 1-8.
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[9] |
NIU Shi-quan.
Lightweight secure memory: Security enhancement for RISC-V embedded microprocessors
[J]. Computer Engineering & Science, 2021, 43(08): 1360-1365.
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[10] |
CHEN Xiang-lan, LI Xi, WANG Chao, ZHOU Xue-hai.
Research on real-time machine model and instruction set with time semantics
[J]. Computer Engineering & Science, 2021, 43(04): 571-578.
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[11] |
XU Zi-chen, CUI Ao, WANG Yu-hao, LIU Tao.
A containerization method for reinforcement learning based on RISC-V architecture
[J]. Computer Engineering & Science, 2021, 43(02): 266-273.
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[12] |
CHEN Wei,WANG Zhiying,CHEN Xuhao,SHEN Li,LU Hongyi,XIAO Nong.
A DICacheBased Hybrid Threaded Interpretation Technique
[J]. J4, 2012, 34(2): 50-55.
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[13] |
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[J]. J4, 2007, 29(6): 84-86.
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[J]. J4, 2006, 28(8): 95-98.
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