Abstract: With the increasing complexity of scientific computing and artificial intelligence algorithms, as the control center of hardware design, the design of instruction flow control components is facing the challenge of increasing complexity and accuracy. FT-xDSP is a 64-bit GPDSP processor independently developed by our company. The design scale and complexity of its instruction flow control components are greatly increased, which makes its verification become a prominent problem. This paper proposes an automatic verification method of instruction flow control based on the instruction rearrangement reference model. Firstly, the abstract model of flow control components is established by taking the instruction input-output relationship as the main feature, which shields the internal complex logic, and reduces the analysis complexity on the basis of ensuring the accuracy of the analysis results. Secondly, by automatically generating random stimulations with constraints, the reference model and the design results to be tested are automatically compared and analyzed, and the code coverage and function coverage are improved when the cost of verification is equivalent. The experimental and practical results show that the method can be used to verify the weak points of instruction flow control verification, which greatly improves the verification efficiency and verification integrity of instruction flow control components.

Key words: instruction flow control, random stimulation, reference model, coverage