Abstract: Designing customized network-on-chip to meet various specific application needs has become the trend of network-on-chip design. Such systems consist of a large number of various types of devices. Mapping these devices into traditional regular network topologies may be able to achieve a lower performance/overhead ratio. Customized on-chip networks become a better choice for domain-specific architecture due to the fine-tuned design feature. However, such fine-tuned design also imposes high burdens on designers which is time-consuming. Therefore, how to explore the optimal custom network topology with agile and fine-tuned design becomes an important challenge  for application-specific network-on-chips. In order to explore the optimal topology of customized network-on-chip, an agile and automatic exploration algorithm is designed. In order to reduce the complexity, a heuristic linear programming algorithm is proposed to accelerate the traversing speed between multiple network layers. Compared with the traditional Mesh topology, the generated topology achieves about 20% performance improvement and reduces the average hop count by about 30% within a reasonable time. At the same time, the design exploration algorithm has low time complexity, which can automatically generate customized network on chip architecture under linear time complexity. It has high scalability and can be applied to large-scale system-on-chip.

Key words: customized network, network-on-chip, topology generation ,