Abstract: The router is a key component of the high performance interconnect network, which can flexibly build a topology with low network diameter, rich routing path and high fault tolerance performance. The hierarchical structure divides the entire router into multiple small subcrossbars. The typical number of sub-crossbar switches is equal to the number of router ports, and each sub-crossbar switch corresponds to an input and output port. The input and output of each subcrossbar are equipped with buffers, resulting in a large number of buffers inside the hierarchical router that limits the scalability. The network structure will be used to build the network topology of the system in a chip, such as connecting smaller switches through a grid, a full interconnect, or a fat tree implemented in a router through integrated circuit technology, which externally appears as a high radix router. Network structures have low costs and require consideration of not only the system network topology’s performance after building the system network but also the router’s own routing issues. This paper proposes a hierarchical structure router based on Clos network, combining the advantages of high performance and low cost of traditional hierarchical structure, and proposes two schedule algorithms for Clos network. In uniform traffic mode, they approach 100% bandwidth utilization, and the RTL synthesis evaluation achieves a maximum area saving of 25.9%.

Key words: high performance computing, interconnection network, network topology, high-radix router, Clos network