Abstract: The implementation of intra prediction algorithms in 3D high efficiency video coding (3D-HEVC) on dedicated hardware has certain limitations, which can not fulfill the need for flexible and autonomous switching among multiple modes of the intra prediction algorithm. This leads to poor encoding performance and low utilization of hardware resources. To address this issue, a novel implementation method of 3D-HEVC intra prediction algorithm on a programmable dynamically self-reconfigurable array processor is proposed. This method, based on the dynamic self-reconfiguration mechanism, utilizes a programmable controller to collect the execution states of the array in real-time and autonomously issue new tasks once the current task is completed. By achieving hardware-level autonomous reconfiguration for different prediction mode mapping schemes, the algorithm can switch flexibly. Compared with related work, experimental results show that while enhancing flexibility, the hardware resources are reduced by 49%, and the computational latency is decreased by 29.2%. When the test sequences are subjected to the entire intra-frame loop test, the results demonstrate good image quality. 

Key words: dynamic self-reconfiguration, array processor, 3D high efficiency video coding(3D-HEVC), intra prediction, parallelization