Abstract: With the development of open-source and agile hardware design methodologies, providing efficient RTL (register-transfer level) simulation support has become increasingly important. The parallel capabilities of GPUs enable the acceleration of RTL simulations by leveraging structural-level and stimulus-level parallelism within RTL simulations. However, due to the presence of feedback loops in timing designs, achieving data-level parallelism within a single testbench remains a significant challenge. This paper proposes a novel method for accelerating RTL simulations using GPUs. The core technologies of this method involve the identification and unfolding of feedback loops in RTL designs, as well as RTL circuit partitioning techniques based on this approach. Circuit partitioning and loop unfolding harness the parallel capabilities of GPUs to accelerate RTL simulations through both structural parallelism and data parallelism within a single testbench. Experimental results demonstrate that the proposed GPU-accelerated RTL simulation method exhibits a speedup ranging from 1.2 to 107.1 times compared to traditional GPU-based RTL simulation methods, and a speedup of 2.2 to 14 times compared to the fastest RTL simulator currently available, ESSENT. 

Key words: RTL simulation, GPU-accelerated, Python register transfer level(PyRTL), hardware construction language(HCL), loop-unrolling ,