• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

计算机工程与科学 ›› 2021, Vol. 43 ›› Issue (07): 1168-1172.

• 高性能计算 • 上一篇    下一篇

一种双端口发射队列及其性能优化

隋兵才,孙彩霞,王永文,郭辉   

  1. (国防科技大学计算机学院,湖南 长沙 410073)
  • 收稿日期:2020-06-09 修回日期:2020-07-20 接受日期:2021-07-25 出版日期:2021-07-25 发布日期:2021-08-16
  • 基金资助:
    国家核高基重大专项(2017ZX01028-103-002);国家重点研发计划(2018YFB0204301)

A dual-port issue queue and its performance optimization

SUI Bing-cai,SUN Cai-xia,WANG Yong-wen,GUO Hui   

  1. (College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)
  • Received:2020-06-09 Revised:2020-07-20 Accepted:2021-07-25 Online:2021-07-25 Published:2021-08-16

摘要: 发射队列是超标量处理器的乱序控制部件,也是处理器中的关键部件,对整个处理器的性能起着决定性的作用。
提出了一种能够有效提高乱序超标量处理器性能的双端口发射队列结构。该队列能够根据指令之间的相关性,估算指令的发射时机,将指令分配到不同的队列中。对比了2种不同的发射策略对性能的影响,输入端标记执行流水线的策略能够获得较高的IPC性能,最大能
提高10.68%。同时对比了采用相同发射策略时,发射队列项数对性能的影响,相比于24项发射队列,32项发射队列能够平均提升2%的IPC性能,最大可以提升8.59%。




关键词: 微处理器, 乱序超标量, 发射队列

Abstract: Issue queue is the out-of-order control unit of superscalar processors, and it is also a key component in the processors, which plays a decisive role in the performance of the entire processors. The paper proposes a dual-port issue queue structure that can effectively improve the performance of out-of-order superscalar processors. The queue can estimate the issue time of the instructions according to the correlation between the instructions, and allocate the instructions to different queues. The impact of two different launch strategies on performance is compared, and the strategy of marking the execution pipeline at the input end can obtain higher IPC performance, which can reach 10.68% at the maximum. At the same time, when the same launch strategy is adopted, the impact of the number of launch queue entries on performance is compared. Compared with 24 launch queues, 32 launch queues can improve the IPC performance by 2% on average, and 8.59% at most.

Key words: micro processor, out-of-order superscalar, issue queue