Abstract: In the era of big data, multi-core processors face significant challenges when handling data-intensive applications, including low data locality, high memory access latency, and inefficient core utilization. Near-data processing (NDP) holds great potential for reducing memory latency and improving computational efficiency. This paper proposes a loosely-coupled near-data processing architecture (LcNDP), deployed at both the shared cache level and memory controller of multi-core processors. The key innovations include: Offloading memory access tasks from compute cores to enable parallel execution of computation and memory operations, thereby hiding memory latency. Processing streaming data via near-data compute units to reduce both computational and memory overhead on the cores. Experimental results demonstrate that, compared to traditional multi-core architectures, LcNDP achieves an average 43% reduction in latency. When benchmarked against conventional NDP-enhanced multi-core designs, it further delivers a 23% average latency improvement.

Key words: near-data processing (NDP), data-intensive application, computer architecture, multi-core processor