一种面向片上互连的自适应通道双缓冲延迟模型

J4 ›› 2012, Vol. 34 ›› Issue (9): 58-63.

一种面向片上互连的自适应通道双缓冲延迟模型

齐树波，李晋文，乐大珩，赵天磊，张民选

(并行与分布处理国防科技重点实验室，湖南长沙 410073)

收稿日期:2010-07-30 修回日期:2010-11-20 出版日期:2012-09-25 发布日期:2012-09-25
基金资助:
国家863计划资助项目（2009AA01Z124,2009AA01Z102）；国家自然科学基金资助项目（60873212）

A Delay Model of Adaptive Channel Double Buffers for OnChip Interconnects

QI Shubo,LI Jinwen,YUE Daheng,ZHAO Tianlei,ZHANG Minxuan

（National Laboratory for Parallel and Distributed Processing，Changsha 410073,China）

Received:2010-07-30 Revised:2010-11-20 Online:2012-09-25 Published:2012-09-25

摘要/Abstract

摘要：

随着集成电路工艺的等比例缩小，互连线延迟相对门延迟增加，导致报文在片上网络路由器之间的传输需要多个时钟周期。但是，在基于信用点流控策略中，物理链路中的寄存器在发生拥塞时不能够缓冲报文。因此，本文提出了一种自适应的通道双缓冲结构，能够在发生拥塞时缓冲报文。通过门级电路的设计和分析，根据逻辑努力方法建立了CDB的延迟模型。延迟模型的准确性利用Synopsys时序分析工具Prime Time在TSMC的65nm工艺库下被验证，两者相差不超过一个τ4。结果表明，在32nm工艺下，1mm长的半全局互连线通道双缓冲(CDB)和简单流水线（SPLS）所需要的级数相同。

关键词: 片上网络, 通道双缓冲, 延迟模型

Abstract:

With the technology scaling down,relative to the gate delay, the global wire delay increases and hence a flit transmission between routers requires several cycles on NetworkonChips(NoCs).Registers in pipelined channels cannot buffer flits when the congestion occurs in the creditbased flow control scheme.Therefore,an adaptive Channel Double Buffer (CDB),which can buffer flits,is proposed in the paper. With detailed design and analysis of the gatelevel circuit, the delay model of the CDB is derived based on the theory of the logical effect.It is validated by Synopsys Prime Time in a TSMC 65 nm technology and found the difference within one τ4.Experimental results show that the depth of the CDB is the same with the SPLS for a 1mm semiglobal interconnect wire in a 32nm technology.

Key words: networkonchip;channel double buffer;delay model

齐树波，李晋文，乐大珩，赵天磊，张民选. 一种面向片上互连的自适应通道双缓冲延迟模型[J]. J4, 2012, 34(9): 58-63.

QI Shubo,LI Jinwen,YUE Daheng,ZHAO Tianlei,ZHANG Minxuan. A Delay Model of Adaptive Channel Double Buffers for OnChip Interconnects[J]. J4, 2012, 34(9): 58-63.

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