The logical effect delay estimation method, proposed by Sutherland I E,can quickly estimate the delay of the logic gates and logic circuits and reduce the difficulty of logical circuits design at the beginning of design.With CMOS technology entering deep submicron, however, short channel effect has begun to affect the correctness of the method of classical logic effort. In order to improve the accuracy of logical effort estimation, the paper proposes an improvement method of logical effort based on the velocity saturation. This method contains two main steps. Firstly, the width ratio of PMOS and NMOS in inverter is considered to precisely estimate the inverter delay, which is normalized. Secondly, logical gate delay is estimated based on inverter delay and velocity saturation. In hspice simulation,32nm、65nm、90nm and 130nm from Arizona State University PTM (Predictive Technology Model), and 45nm from North Carolina State University FreePDK are used. Comparative experiment demonstrates that our method improves the accuracy of the NAND gates delay estimation, approximately by 10%.
